Just a quick question here…
I’m placing the components for my TinyFPGA based stepper motor controller board (see the prior articles here first, here next, and here last). Specifically, I’m finding places for all of the capacitors. That’s where the question of schematic style comes in. 
When I first started using CAD software, sometime shortly before the stegosaurus roamed the land, I would position component symbols on the schematic near the chips they belonged with. Doing so made it easy, come layout time, to remember which capacitors go where.
Since then, though — and I don’t remember when I started this — I’ve started following the practice of grouping capacitors on the schematic, as I’ve done on this sheet to the right. All of the capacitors are up at the top, shown connected to V+ and ground rails.
That’s not a problem when they’re all 0.1uf bypass capacitors and each chip just takes one. However, with higher speed and more complex chips, multiple bypass caps or different values are often required on each chip.
Now, when I go to layout, I need to go find my component data sheets again (they really should never be very far away) and re-figure out what combinations of bypass capacitors go to which pins on what chips.
I like the cleaner schematic that results from grouping bypass caps, but it’s adds pain and a bit of opportunity for error during layout.
What style do you use and why? Am I an idiot for doing it this way? Wait. Don’t answer that last question.
Duane Benson
Six of one and 12 × 5 × 10-1 of another
As you say, it’s a matter of style, but what happens when you’ll need to check the schematics at a later date? This is the main reason why I place the components, as similar as logically possible, to the layout.
I sort of like grouping all of the power connections in one place. That includes all the bypass caps and the chip connections (this means using two or more symbols per chip). You can annotate the cap properties as to which chip it is associated in one of its extra property fields, keeping that field as not visible.
Also I like placing pin headers with the headers at the border and the conductors pointing in. If you slide the chip pins around on the chip, you can connect the header pins directly to the chip and avoid searching for the net labels. This does mean you do have a multiplicity of symbols for the same chip in your library.
BTW Farads?
I follow a convention I developed many years and CAD systems ago. I have a “chart” which functions sort of like an index of all ICs sorted by reference designator. There are columns for pin numbers and net names for all powers and grounds. In the chart are also columns for bypass capacitor reference designators (and their values). Those columns actually represent real schematic capacitors. Embedded in the lines of the chart are the pins for the actual capacitor and nets connected to the pins carrying the signal names as mentioned above. If it is a large schematic (many pages and components), the chart is either on the first or last page. It’s sort of hard to describe in words, but the chart is very easy to understand. Unfortunately, some people don’t like it because they can’t see real capacitor symbols. When a schematic has 100 or more capacitors it can get cluttered real fast. In that case the chart really clears up a lot of space.
I like the clarity of grouping the bypass caps off to the side, but it does seem to cause problems when I go back to a schematic after a while. I’ll probably end up with a hybrid style of some sort.
@Felix – For some reason my CAD software was defaulting to exponential notation for capacitors so a 0.1uf is shown as 1e-07F. I can change them individually, but haven’t yet dug around to see how to change the default notation.