Category Archives: Laying It Out

Off-grid thoughts from a burned-out designer turned editor.

Via Shifting

Posted on by

Here’s an example of what via in pad can do for a small passive component. Other things can happen too, like tombstoning or twisting. But take a close look at this photo. In doing so, you’ll note that both sides of  Small fillet passive via in pad the part are soldered down. Sure, it’s shifted, but who really cares? It’s electrically connected. Right?

In this case, much of the solder on the lower pad flowed into the via. This led to an imbalance in surface tension between the two pads which shifted the part. Some logic might say that since both ends of the part are soldered in and there aren’t any shorts, it’s all cool.

It is all cool because it’s been out of the reflow oven for quite a while, but it’s not cool because it’s not good workmanship. The IPC created standard IPC-A-610 for just such an issue. Class I is the loosest. This might pass that. I’m not sure though because we don’t do anything with Class I here at Screaming Circuits except reject it. Class II is the typical commercial type standard and this shall not pass that standard. Nor would this pass Class III, an even tighter workmanship standard for higher-reliability requirements.

That’s the real issue: reliability. With a good, symmetrical solder joint, you not only have a good electrical connection, but you also have a reliable mechanical connection. It will resist flexing and thermal expansion stress. This one may not. Give it some good thermal cycles or bounce it around in a race car engine computer and you may find yourself sidelined.

The moral of the story is to keep those vias out of your pads; even with passive components. Or, put the vias there but fill and copper plate them at the board house.

Duane Benson
Balrogs in pad are bad too

http://blog.screamingcircuits.com/

Fun with Electrolytics

Posted on by

I was fiddling with one of my robot boards the other day — popping some passives on and off and checking out subs and alternate values. I was doing this on a couple of boards at the same time. Everything was going along fine until I started to do a power-on test. The first board was fine. The second one would briefly light the power indicator LED. It would start a full brightness and then fairly quickly fade out.

My first thought was that I had been too aggressive with my soldering iron and had burned something out. (Who has already guessed what really happened?) Turns out, that wasn’t the case. I put it aside and came back to it a few days later. This time, I gave it the finger test and discovered that my regulator was hot. Darn. Next, I found a hot tantalum cap. Nothing looked out of the ordinary/ I stared at it for a while. The + side was on the left in both parts and… The plus side was on the left in both parts. One was supposed to be on the right. Oops. The cap had a high enough voltage rating that it didn’t blow up. It just pulled down the supply until the over-current protection in the regulator shut it down.

I’ve heard a number of folks recommend that you keep all your polarized parts facing the same way. It’s not always possible, but it can certainly reduce opportunities for errors like I made here.

Duane Benson
Left, right. Left, right. Left, right. Left, left. Left, right …

http://blog.screamingcircuits.com/

So Long, Old Friend

Posted on by

Just watching the final shuttle launch and pondering a few questions.

A significant number of innovations came out of the Mercury, Gemini and Apollo programs and filtered down to public life. Some were in materials, some were in electronics, some in software algorithms  and some in other technology areas. It was pretty much all new back then. When the shuttle was first being developed back in the 1970s, innovation in materials and other areas came about as well, though it did use a fair amount of recycled technology in the beginning.

But since that time, have there been any major breakthroughs directly from the shuttle to filter down? Though it never lived up to the “one launch a week” billing, it did, in a sense, become the space “truck.” Sort of an old pick-up truck. Not much new. The occasional upgrade. The occasional breakdown. But mostly just there hauling stuff around.

When the next manned launch vehicle comes out, will it deliver a wealth of innovation as did the first decade of manned space flight? Or will it be designed with primarily off-the shelf or near off-the-shelf technology?

In the 1960’s, private industry benefited greatly from the research that went on in the space program. I suspect that the next time around, whether it’s a NASA design or a commercial design, it will be the other way around and the space vehicle will benefit from research paid for by commercial activities.

Duane Benson
Thanks for all the fish

http://blog.screamingcircuits.com/

Family Reference

Posted on by

I’ve written a bit about reference designators here and there. There are a few more factors that we run into now and then. Take the family panel. In case you aren’t familiar with the term, it means that you have several different designs laid out into in one panel, as opposed to multiple copies of the same design in one panel.

Using a family panel can be a convenient way to deal with a multi-board design and can sometimes save a bit of money. Just a caution, though. Make sure to check with your fab house first. Some don’t like family panels and some won’t separate them for you. If you do have them separated prior to assembly, either at the fab house or by you, then you don’t have any reference designator worries.

If you leave them in the panel and wish to have them machine assembled, it can get a bit more complex though. “Why?”, you say. I’ll tell you why. Generally, most people start at “1” for each new design. i.e. “D1, D2, D3… R1, R2, R3…” If the boards go into the machine independently, that’s no problem. However, if you send the panel into a smt assembly robot, it may very well see that as your board having multiple D1’s, R1’s, etc. That would be rejected as an error in most cases.

If you are using the family panel approach, don’t restart your numbering when you move to another one of the designs that will be in the panel. Either continue on from the last number in the prior design, add in a hundred’s, with each design getting a different hundred’s number or add a unique suffix on each board.

  1. Wrong way: PCB1: “R1, R2, R3, R4, C1, C2”. PCB2: “R1, R2, R3, R4, C1, C2”.
  2. Right way: PCB1: “R1, R2, R3, R4, C1, C2”. PCB2: “R5, R6, R7, R8, C3, C4”.
  3. Right way: PCB1: “R101, R102, R103, R104, C101, C102”. PCB2: “R201, R202, R203, R204, C201, C202”.
  4. Right way: PCB1: “R1A, R2A, R3A, R4A, C1A, C2A”. PCB2: “R1B, R2B, R3B, R4B, C1B, C2B”.

There are a lot of ways to do this. Just make sure that no reference designators are repeated from one board design to the next. I prefer method #3 myself.

Duane Benson
Is it immediate or extended? Does it matter?

blog.screamingcircuits.com

Via Current Capacity

Posted on by

After my blog item last week, Michael asked a question about my Via in Pad Myth #5. He asked:

I have a question about vias. I have seen charts on the current carrying capacity of traces, but what about vias?

That’s a good question. I’ve heard that you first need to know the thickness of the via wall. Then, once you know that, you can calculate the trace-width equivalent for the via by using the formula for the circumference (diameter X pi ). For whatever number that gives you, compare the closest smaller trace width.

Via cross section My related questions to all of you PCB fabrication gurus out there are:

Since vias are not created in the same way as the trace plating is, can that simple formula be used? While the trace copper is laminated onto a nice smooth PCB surface, the vias are typically created by deposition of copper dust in the via and then electroplating more copper. Then the surface finish is applied to all of the exposed metal. The via walls would generally be rougher than the flat substrate surface. Does that have an impact on the current capacity of a via?

Further, since airflow will be somewhat restricted in a via relative to a surface, should the via effective width be compared to an internal trace instead of an exposed surface trace? Should it be a compromise between the two?

If you look closely at this via cross I pulled from Wikipedia, you can see that the via wall looks to be thinner that the traces. You’ll have to make sure that your board fab house can give you an accurate thickness of the via wall.

Duane Benson
If you know the via current capacity, can you calculate the past and future capacity?

http://blog.screamingcircuits.com/

Random Via-In-Pad Myth #5

Posted on by

Myth #5: When you need thermal vias, more is better, bigger is better

Hmmm. Logically, this would seem to be the case. There are limits though; especially if you want a reliably assembled product. Older parts with heat slugs easily accessible for bolting on heat sinks didn’t have this issue. Just bolt on a piece of metal and maybe blow a fan across it. It’s different with a lot of the new, Padinvia smaller surface mount packages. Many have a heat slug on the bottom, which requires carefully placed thermal vias to a copper pad on the underside of the board.

An extreme case of flooding the land with vias can be seen in this illustration here on Padinvia_alt the left. In terms of assembly, you can hack this together for a prototype, but it’ll never fly in a production environment.It would be much better to use fewer smaller vias and have the center land covered with solder mask except where the metal on the chip is exposed, as in the illustration on the right.

Duane Benson
Place one carrot seed in each via and cover it with planting soil

http://blog.screamingcircuits.com/

Loopy Ground Loops

Posted on by

A while back, I posed a question about using flood fill (AKA copper pours). I’ve been reading a lot about ground loops lately which brought me back to that original question.

LED scroll ground plane Some people suggest segmenting your ground plane between analog and digital sections. Some people suggest segmenting the ground plane for individual critical ground return paths. The follow on to my original question is: On non-exotic designs does segmenting ground planes really help? There’s actually two questions, with the second being: At what clock speed does it make sense to start worrying about issues caused by ground return paths/ground loops? There are probably more questions. Those are just the two rattling around in my head at the moment.

Interestingly, though, when I wrote the original post, there didn’t seem to be a clear “most common” between pour and no pour PCBs. Today, I’d have to say that the majority of designs we see here at Screaming Circuits do use flood-fill ground planes, either internal or external.

Duane Benson
You can solve ground and noise problems by just not hooking up power

http://blog.screamingcircuits.com/

Package Variants

Posted on by

Cap under connector footprint Here’s another issue we see from time to time involving the old, familiar, 0.1″ pitch headers. Break away header When initially laying out the board, the footprint for the break-away header is used. It’s small and easy to use. The headers are cheap and easy and you don’t need to stock a bunch of different pin-counts.

That’s all fine and dandy until the next rev of the prototype when you decide to change to a shrouded header for the additional reliability and pin protection afforded by it. When making that change, don’t forget that the footprint with the shroud may very well be bigger than the break-away footprint.

Shrowded header In this particular case, it wouldn’t have mattered except for the capacitor that ended up under the shrouded header.

Duane Benson
Get out of my cap’s space, man

http://blog.screamingcircuits.com/

And the Race Goes On

Posted on by

AUP package The race for the smallest part is still going strong. That and the fact that basic logic gates are still with us is affirmed quite well with a new set of chips from NXP. The 74AUP2G00 is a dual two-input NAND gate in a no lead XSON8 package at just 1 x 1.35mm. That’s not the scary part. The scary part is the lead pads under the part are 0.15mm wide and just 0.35mm pitch center to center. That’s 0.0059″ and 0.0138″ respectively. The gap between the pads is 0.2mm (0.0078″).

To put that in a little bit of perspective, an 0201 passive component is 0.024″ x 0.012″. An 01005 is 0.016″ x 0.008″.

Above is a land pattern for the part with an 0201 bypass cap next to it. The trace going from the pin to ground (Pin 4) is an 0.008″ trace. The trace going to VCC (pin 8) is 0.006″. The via is a pretty standard 0.024″via. As you can see, an 0.008″ trace and space isn’t going to do for a board with this size of part on it. Even 0.006″ is really a bit too big.

Duane Benson
La de da de de, la de da de da

http://blog.screamingcircuits.com/

Day 2: Custom Parts

Posted on by

Moving on from where I left off a few days ago … I was planning on using the PIC18F2320, but in poking around, I found that the PIC18F2321 is about $3.00 less expensive in small quantities. I’m not entirely sure why. They’re virtually identical. The 2320 does have two 8-bit timers instead of one in the 2321, but I haven’t spotted any other differences that would matter to me in this case. The 2321 has lower sleep and idle currents but I don’t think that matters in this application either.

PCB123 PIC partial sch PCB123 doesn’t have the 2321 in its library. I could just use the 2320 part, but to get full use out of the pricing and availability features, I’ll have to customize the part so that the BOM tool can find it at DigiKey.

I had the “place component” box up already, so I just clicked on “Manage Parts” and started filling in the information in the middle column of the dialog. The I clicked the “Select Simple” button, searched on “2320” and selected the symbol for the PIC18F2320-I/SO. So far, so good.

PCB123 manage parts dialog Now, the question is: do I select “Apply Changes” or “Create a New Part?” This would be easier if I actually looked at the documentation or something, but am I doing that? Of course not. I’m going with “Create a New Part.” Oops. Needed to select or generate the footprint first. Do that and search on “SOIC” and pick out an SOIC28, “Create New Part” and save it in a Library. I picked “Microchip.”

Done. Now when I go back to the Insert / Add Part function, I search on PIC18F2321, and there it is. Apparently, I did it right, because the BOM tab will find it and show price and availability at DigiKey.

Duane Benson
And, today, it’s not just a rain cloud, but a full one

http://blog.screamingcircuits.com/