AT Tiny is Tiny

ATTINY44A-MMH I just spotted a note on Twitter, from SiliconFarmer, referring to the ATtiny44A coming in a 0.45 mm pitch QFN as well as a 0.5mm pitch MLF package. (In practice, an MLF is the same as a QFN, by the way.) (Just in case you actually care, we’re on Twitter at “pcbassembly.”)

I’ve run across a number of 0.4 mm BGA packaged parts, but this is the first sub-0.5 mm QFN I’ve seen. Interesting that they have two different sizes of QFN package, one at 4 x 4 mm and the other at 3 x 3mm. If you’re that tight on space, that little 7 square mm of extra open area can make a difference.

Screaming Circuits won’t care on the assembly floor. We do plenty of 0.4 mm parts so a 0.45 isn’t anything new. The most important thing to remember is to use the right footprint. It’s easy enough to accidentally use a QFP footprint when you have a QFN (like here). I could see it being even easier to swap for the wrong footprint with this part. Doing so would be bad, most certainly. You might get one or two contacts per side on the right footprint, but that’s pretty much as good as none.

Duane Benson
It’s like Ice-9. The same, only different.

http://blog.screamingcircuits.com/

Little Chippy Challenges

And “chippy,” in this context, refers to chip caps and any other tiny two-connector components. When considering surface mount, most people think of the many-connector parts, like BGAs and QFNs as the challenging components. That’s mostly true. However, the little passives can be big bears too if not treated properly.

Two part tombstone You could have tombstoning problems. This can be caused by unequal sized pads, unequal sized traces going to the pads or inequality in copper plane in a different layer. A big part on one side can cause tombstoning too — the big part’s thermal mass may slow the solder paste melt on one side of the part, leading to tombstoning.H Skewed passive via in pad

Via-in-pad is still a problem too. Open vias can lead to unreliable connections, tombstoning or crooked  parts.

Soldermask tombstoning for blog Solder mask can cause problems too. Too thick a solder mask can prevent the part from reaching the solder and can cause tombstoning. Too think a solder mask can also interfere with outgassing in the reflow oven which can cause solder ball splatter. (A = okay, B = not okay).

Duane Benson
It just goes to show you…
It’s always something.

http://blog.screamingcircuits.com/

Electronics Shelf Life

Do parts and PCBs have a shelf life? Well, yes and no. I have some 7400 series logic chips in DIP form that I bought back in 1980. Every now and then, I pull one out and put it into a proto board to test some circuit idea I’ve got. They still work thirty years later. I haven’t taken any special care in storage either. Some are stuck into anti-static foam. Some are not. All are sitting in a mini-parts bin without any moisture protection. I guess they do get a little shielding from light, but basically, they’re just hanging out. They’ve been, at various times, in the attic, in the basement, in the garage or in the house.

That may seem like good evidence refuting a shelf like for parts. And today’s parts are even more robustly Bent pins in strip designed to start with. Still though, if I use any of those parts, it’s generally in a proto board or a socket. Sometimes I have to straighten the leads a bit. A lot of things don’t matter so much at low temperatures, low speeds, low volumes and large geometries.

It’s different when you have fine pitch parts being picked up and placed by a robot and then run through a 10-zone reflow oven. Oxidation that doesn’t matter for a socketed prototype can interfere with the solder adhesion. Bent pins or missing BGA balls can prevent the part from fitting. Moisture absorbed over time can make the chip act like a popcorn kernel when in the reflow oven.

That’s not to say that you can’t use old parts for a prototype these days. Just give them a good inspection before sending them off for assembly. And, if they’re moisture sensitive parts or have been stored in high-humidity areas, consider having your assembly house bake them before assembly. The same goes for raw PCBs too. Overly moist PCBs can delaminate during reflow. Some PCB finishes such as immersion sliver and OSP can tarnish or degrade over time too.

Duane Benson
Archaeologists, we are not

http://blog.screamingcircuits.com/

PCB Planarity, Not Polarity

Via-in-pad can ruin a manufacturer’s whole day. Or, if properly done, can go completely unnoticed. There are a number of ways to properly put a via in a pad but the best is to have it filled and plated over at the board fab house.Copper filled via bulge

Copper filled via droop If you do that, check with them on their planarity standards. If they don’t hold tight, you can end up with a  dip or a bump where the via is. Neither of those are as big a  problem as an open via, but they can still lead to some difficulties.

Speaking of bumps, the old standby, HASL, generally leaves bumps on the pads too. And, across the span of a BGA, the bumps can vary in size and shape. That’s not such a good thing either. If you’re designing with a fine-pitch BGA, you might want to consider a flatter surface such as ENIG or immersion silver.

Duane Benson
Fight Uni

Pad is as Pad Does

I’ve recently written a bit about solder mask and pads relative to BGAs. In most cases, we recommend NSMD (Non Solder Mask Defined), or copper pad defined, pad for BGAs. With the BGAs, the NSMD pads will permit the BGA to sag just a bit more and adhere to both the top and the sides of the pad, resulting in a better mechanical connection. The exception seems to be 0.4mm pitch BGAs with a straight matrix alignment as in the illustration the link above. TI, with its Beagleboard project, found that NSMD pads tended to lead to bridging and had much better results with SMD pads. Staggered BGA lands should still use NSMD pads though.

Along with the 0.4mm BGAs, not all parts need or want NSMD pads. International Rectifier has a package called “DirectFET” which is designed to use solder-mask-defined layouts. In this package, the FET source and gate connections are directly on the FET die. The drain connection is a plated copper can directly bonded to the drain side of the silicon die. This system gives a very low-loss capable part with great thermal conduction properties.

Internal Rectifier recommends solder-mask-defined pad layouts. Take a look at their application note 1035 for complete details on designing with this package. I might try the form-factor out myself some time. It always bugs me that a 100 Amp MOSFET might only, in practice, be able to pass a small chunk of that amount of current because the leads or internal interconnects would otherwise melt. The DirectFET package should aleviatemuch of the melting problem.

Duane Benson
Melting is good if you’re talking about toasted cheese

http://blog.screamingcircuits.com/

Missed It by That Much …

Yucky brd C6 Running a DRC (design rule check) before sending your PCB out for fab and assembly is a must. It’s also a minimum. Not everything is caught by all DRCs.

For example, if you look at these PCB images, you’ll undoubtedly spot the problem right away. These passed the Eagle DRC. I’m not saying all CAD packages will miss this kind of thing, but you should always expect that something might get through. Yucky brd I2C

Of course, if you end up selecting the wrong component footprint, or if the footprint library part was created incorrectly, the DRC definitely won’t catch it. A DRC also won’t likely help if you output your Gerbers incorrectly, i.e., positive output vs. negative output.

Just like you don’t completely trust an autorouter, you shouldn’t completely trust your CAD packages ERC and DRCs. Spend a little time manually double-checking things too.

Duane Benson
Bring out the cone of silence

http://blog.screamingcircuits.com/

Scoopage

I wrote recently about segmenting your solder paste stencils for the big open areas on your QFNs. The idea is that if the entire area is left open, it may end up with too much solder in the heat slug area, causing the part to lift up and not solder properly.

QFN center void CadstarGuy commented: “Also — when you have the full aperture in the stencil it can tend to drag as it is pasted leaving big gaps in the solder (and excess solder on the screen).”

That’s a very important point to remember. Ironically, leaving the area fully open can lead to either too much solder or not enough solder. Weird. Huh? The solution is the same: segment your stencil layer inside that center pad area.

Duane Benson
Anoid the void!

http://blog.screamingcircuits.com/

Spam, Spam, Eggs and Spam

I normally expend most of my writing words on challenges our customers and other engineers might face in their day to day design and layout activities. But not today. Today, it’s about a specific challenge faced by your typical blogger. Off and on for the last couple of weeks, I’ve come into work in the morning, opened up the blog and found three spammy comments. Here’s today’s three:

“Compare to the majority of the other blogs, your site tend to be so fantastic. Therefore nice to examining the post. If I’ve a probability, I would like to research along with you because I think that my potential haven’t yet achieved the excellent amount.”

“You may remember the three proverbs: Laugh, and the world laughs with you; Weep, and you weep lone. Life is measured by thought and action not by time. Long absent, soon forgotten.”

“You may remenber [sic] the three proverbs: Laugh, and the world laughs with you; Weep, and you weep lone. Life is measured by thought and action not by time. Long absent, soon forgotten.”

Now, it is a bit flattering to hear that my site tend to be so fantastic. Not just “fantastic,” but “so fantastic”! But perhaps the subject matter could be a bit more on topic. The author noted that if he have probability, he would like to research along with me. I could always use some extra help, but I don’t have any probability to pass on. Perhaps a call to Zaphod would be in order.

I’m not sure I agree completely with the second supposition. I’d bet that a lot of unemployed or underemployed folks are weeping right now. Probably enough that they could be considered to have a world weeping with them. I know I would. I’m also not sure what the deal is with the third one. That author just copied from the one above it. How rude.

All is not always as it seems though. After reading these this morning, I did as I always do and fed the three comments into my netlist confabulator. It turns out that the text in these three comments is actually a turbo-encoded form of the design of the Constellation spacecraft. If I had checked the IP address prior to marking the comments as spam, I wonder if I would have found that this is a desperate rocket scientist tying to smuggle his decade of work home before the lights go out and the servers get recycled.

Duane Benson
Have you got anything without spam?

http://blog.screamingcircuits.com/

Random Via-in-Pad Myth #7

Myth #7: In regards to via-in-pad, all PCB finishes are the same

Ant_wideweb__430x317

Well, it might seem so, but let’s look a little closer. No. Not that close. Back the camera up a bit.

Here’s a good example: In some cases, it’s okay to seal off the via with soldermask on the opposite side of the board. It’s not the optimal way to do it, but when the geometries aren’t that small, it can work. It needs to be a part where voiding isn’t an issue, because the solder may still go down the via and cause some of those voids. “Void” may be accepted in C code, but it’s usually bad form in a PCB.

Getting back to the subject… Immersion silver gives a nice smooth surface. It’s fairly easy to solder and provided the boards are used promptly or stored properly, it’s a good RoHS choice.

BGA via in pad Silver But, it’s not a good choice for a situation where you cap a via with soldermask on the underside of the PCB. The immersion silver finish will likely out-gas a bit and when contained, as in the sealed off space between the solder on the top and the soldermask on the bottom, that outgassing can be corrosive and lead to reliability issues sometime during the life of the product. So if you do need to have vias that are capped on the bottom side, you should consider a surface finish other than immersion silver.

Duane Benson
No more silver on Walden Pond

http://blog.screamingcircuits.com/

Window Pane Is Not a Pain

QFN parts (also known as MLF or micro lead frame) used to cause a lot of problems a few years ago, as evidenced by the number of blog posts covering the subject.

Can I use my own blog as cited evidence to justify my conclusion? Doing so is probably bad form, but I’m doing it anyway. Interestingly, if you look up “citations” in Wikipedia, the entry (as of this writing) has a note indicating that the article on citations has insufficient online citations. Hmmm.

Screaming_QFN_Fig1 Anyway, it seems that the industry in catching up with the proper manufacturing methodology for use of the technology. It’s important enough though that it bears repeating now and then. The key to successful QFN and DFN manufacturing really is in the solder paste stencil pattern. Consult the data sheet for the part, but if you can’t find the datasheet or if it doesn’t cover the stencil layer, use the window pane technique, or “segmenting” for the stencil layer when you’re making the library part for your CAD software.

Good QFN stencil b

If you leave the full thermal pad area fully open, you’ll most likely end up with too much solder in that area. The part will ride higher than it should and may very well float too high for all of the pads on the  side to connect. See the top  part on the above illustration.

Shoot for 50 – 75% paste coverage by segmenting the stencil as in this illustration on the left here. That’ll ensure that the center pad and the side signal lands will be at the same level. You’ll get much better yields and reliability.

Duane Benson
The strangest sight I’ve ever seen
2 buffaloes, 2 buffaloes, buffaloes on my lawn.

http://blog.screamingcircuits.com/