I’ve described the optimal way to create your land and solder paste layer for QFNs a couple of times before. But that was for a standard square QFN or rectangular DFN. What happens if you look at the bottom of your QFN and it’s all weird like this one?
Does it require a different philosophy for the big pad areas? Should it just be a solid opening because their is more than one thermal pad and they don’t cover the whole area?
Well, the image is an Intersil ISL8200 power module. It’s pretty cool and Intersil was kind enough to actually put the paste layer recommendations right in the data sheet. Unfortunately, not all chip manufacturers do that.
The bad news is that it’s a pretty complex pattern. The good news is that the data sheet gives a diagram with great detail on the required dimensions for the lands and the stencil. And, yes, you treat this just like any other QFN thermal pad. They recommend 50 – 80% paste coverage for the thermal pads just like everyone else. That means that you’ll segment the paste cut-outs in the paste layer for each of the four thermal areas just like you would for the whole pad area on a standard QFN. The data sheet for this part has the specifics.
For similar parts from other manufacturers, you should go to their datasheets and app notes first, but if you don’t find a recommendation, we would suggest doing the segmenting and shooting for somewhere between 50 and 80% coverage. Putting down too much paste is a bad idea for any QFN or DFN, but it’s probably even more critical with a part like this where the solder areas only cover half the part. If there’s too much solder on the underside, it will likely tilt and most likely not solder reliably.
Duane Benson
Don’t eat paste.
Duane,
Get used to these unique one-of-a-kind component packages. I just got a datasheet for a pull-back lead QFN that has 8 different lead sizes on different lead center pitches. I wish I could post the picture here.
It’s good that the component manufacturer provides a recommended land pattern, but the duplication of effort building the CAD library part is staggering. The time spent to create this CAD library part would range from 1 – 3 hours depending on which CAD tool you use (average 2 hours).
Now imagine that 10,000 companies worldwide design this component into their electronic product. That’s 20,000 man hours of duplication of effort for a single component. Can you imagine this going on with 50% of all new CAD library parts that you have to build today? CAD library construction is becoming increasingly more difficult with each new design.
Rather than the component manufacturer providing the datasheet information they should instead provide the CAD library part in every CAD format to eliminate the 20,000 hours of duplication of effort. The technology is available to build the CAD library part once and automatically translate the library part to every CAD tool format. Build it once, build it right and never build it again is my motto.
I can help Intersil accomplish this but I don’t know who to contact in these large component manufacturers. I’d be glad to actually create the CAD library parts for Intersil in every CAD format for their customers to freely download or I could provide Intersil the tools for them to do it themselves. They just need to follow the IPC-7351B land pattern standard so that their CAD library parts match the rules for consistent quality. i.e.: it would not help anyone to download a free library part unless the quality was consistent with everyone’s existing CAD library.
Intersil could have built the CAD library parts in less time than it took them to create the datasheet with all the dimensional data. We don’t want datasheets, we want CAD libraries.
Tom Hausherr
Mentor Graphics
EDA Library Product Manager
Well said Tom.