Jiangsu Xiehe Electronic started trading today on the Shanghai Stock Exchange. The company makes flex circuits and performs SMT. That should be a big deal, since PCB manufacturers going public has become a rarity.
This is not your father’s printed circuit industry. IPOs are a novelty in our industry these days.
Moreover, almost all the IPOs of fabricators or EMS companies in the past 10 years have been in Asia.
Stretching back over the past decade, there are a few nuggets. But just a few.
Shennan Circuits (2017 IPO) and Zowee Technologies (2010) are public on the Shenzhen Exchange, and OK Industries (2017) is traded in Japan. And Dixon Technologies debuted in 2017 on the India Exchange.
Over in the UK, fabricator Trackwise Designs had an IPO in the UK a couple years ago. And NCAB went public in Sweden.
As private equity firms continue to consolidate fabricators and (mostly) EMS companies, as New Water Capital did with Veris and Saline Lectronics this week, the question becomes, what is their end-game? Will they amass enough revenue through M&A to make a public offering viable? Or will they try to button it up and sell to another PE firm — or perhaps an even larger manufacturer?
And is the era of the publicly traded circuit board manufacturer winding down?
Here are the answers to theSMT IQ Test of a short while ago.
What does the “A” in SAC305 stand for? ANSWER: SAC stands for tin (Sn), silver (Ag), and copper (Cu). The “305” indicates 3.0 percent by weight silver, 0.5% copper, and the balance (96.5%) tin.
The belt speed on a reflow oven is 2 cm/s. The PCB with spacing is 36 cm. What is the maximum time that the placement machines must finish placing the components on the PCB to keep up with the reflow oven? ANSWER: Time (s) = product length (cm)/belt speed (cm/s) = 36 cm/2 cm/s = 18 sec.
In mils, what is a typical stencil thickness? ANSWER: In range of 4 to 8 mils.
BTCs are one of the most common components today; a subset of BTCs is the QFN package.
What does BTC stand for? ANSWER: Bottom terminated component
What does QFN stand for? ANSWER: Quad Flat Pack No Leads.
What is the melting temperature of tin-lead eutectic solder? ANSWER: 183° C.
In mm, what is the finest lead spacing for a PQFP? ANSWER: Most common is 0.4 mm. A few have 0.3 mm, but these smaller spacings are hard to process.
Are solder pastes thixotropic or dilatant? ANSWER: Thixotropic; the viscosity of solder paste drops when it is sheared (i.e forced through a stencil). Dilatant materials stiffen when sheared.
In stencil printing, what is response to pause? ANSWER: When stencil printing is paused, the viscosity of the solder paste can increase; this situation would be considered a poor response to pause. Pastes that have stable viscosities during pausing are considered to have good response to pause.
For a circular stencil aperture for BGAs or CSPs, what is the minimum area ratio that is acceptable? ANSWER: Typically greater than 0.66, although some solder pastes can print well a little lower than this.
What are the approximate dimensions of a 0201 passive in mils? ANSWER: Approximately 20 by 10 mils.
The High Density Packaging User Group has named Larry Marcanti executive director, ending Marshall Andrews’ 15-year run as head of the trade consortium.
Larry is an excellent choice. He has a degree in chemical engineering, and has more than four decades’ experience in the printed circuit board industry with Honeywell, Nortel and Avaya, including the eight spent in various levels of involvement at HDPUG. He knows the industry needs inside and out, and will get things done.
But let’s give Marshall his deserved due. He is perhaps the most experienced technical consortia executive this industry ever had. From MCC to ITRI to HDPUG, Marshall had a hand in all the major nonprofit research groups affecting printed circuit boards and packaging.
Many folks step in and out of the trade group participation. Marshall was a lifer. His legacy will last for years.
Mary had worked at a small SMT “mom and pop” shop for 12 years. Business was always good and she moved up to CFO of the 60 person company. Revenue had been over $12 million for a few years with profits north of $1 million each year. She marveled how well Fred, the owner, managed the small firm. As CFO, she was well aware of the strong financial strength of the company.
Mary was stunned when 18 months ago, Fred said he wanted to retire in less than two years, and he wanted her to “buy him out.” Fred was fit and spunky, but 75 years old was now in the rear view mirror.
Mary was more than stunned by the price Fred wanted; it was way, way too low. She even “complained” about this. But, Fred considered her more as a daughter and insisted on the low price. However, one of the concerns they both had was that Fred was really also the chief engineer. They had many loyal workers, as Fred paid 50% over the local rate and provided great benefits, but no one could fill in for Fred in the technical aspects of running the shop.
Fred had been trying to coach Mary for the past 18 months so that she would understand the technical aspects of SMT assembly better. Mary was a fast learner, but with only 6 months left before Fred’s retirement, they both agreed they needed to hire a chief engineer.
So, Fred developed an SMT IQ Test for the candidates. If they could not get at least 80%, they would not be considered. Fred argued that if you were really good enough, you had to know 80% of these questions. Here they are:
What does the “A” in SAC305 stand for?
The belt speed on a reflow oven is 2 cm/s. The PCB with spacing is 36 cm. What is the maximum time that the placement machines must finish placing the components on the PCB to keep up with the reflow oven?
In mils, what is a typical stencil thickness?
BTCs are one of the most common components today. A subset of BTCs is the QFN package.
What does BTC stand for?
What does QFN stand for?
What is the melting temperature of tin-lead eutectic solder?
In mm, what is the finest lead spacing for a PQFP?
Are solder pastes thixotropic or dilatant?
In stencil printing, what is response to pause?
For a circular stencil aperture for BGAs or CSPs, what is the minimum area ratio that is acceptable?
What are the approximate dimensions of a 0201 passive in mils?
Soldering enables modern electronics. Without solder, electronics would not exist. Copper melts at 1085°C, yet with solder, we can bond copper to copper at about 235°C or less with current lead-free solders. These lower temperatures are required, as electronic packages and PWBs are made of polymer materials that cannot survive temperatures much above 235°C.
Before the advent of RoHS, tin-lead solders melted at about 35°C less than lead-free solders. So today, soldering temperatures are at the highest in history. For some applications, it would be desirable to have solders that melted at closer to tin-lead temperatures. This desire has increased interest in low-melting point solders, such as tin-bismuth solders. Eutectic SnBi melts at 138°C, so reflow oven temperatures in the 170°C range can be used. These lower reflow temperatures are easier on some fragile components and PWBs and will reduce defects such as PWB popcorning and measling. However, the lower melting point of SnBi solders limits their application in many harsh environments, such as automobile and military applications. As a rule of thumb, a solder should not be used above 80 to 90% of its melting point on the Kelvin scale. For SnBi solder, this temperature range is 55.8 – 96.9°C. These temperatures are well below the use temperature of some harsh environments. In addition, SnBi solders can be brittle and thus perform poorly in drop shock testing.
So, the electronics world could use a solder that can reflow at a little over 200°C, but still have a high use temperature. This situation would appear to be an unsolvable conundrum. However, my colleagues at Indium, led by Dr. Ning-Cheng Lee, have solved it. They used an indium-containing solder powder, Powder A, that melts at <180°C and combined it with Powder B that melts at ~220°C. By reflowing at about 205°C, Powder A melts and Powder B is dissolved by the melted Powder A. To achieve this effect, the 205°C temperature must be held for approximately two minutes. The remelt temperature of the final solder joint is above 180°C. I discussed the phenomenon of a liquid metal dissolving another that melts at a higher temperature before. An extreme example of this effect is mercury dissolving gold at room temperature. So, don’t drop any gold or silver jewelry into a wave soldering pot and expect to fish it out an hour later!
Powder A would not be a candidate on its own as it displays some melting at 113°C and some at 140°C.
Using the criteria above, the use temperature of this new solder powder mix can be in the 89.4 – 134.7°C range, after reflow, as the remelt temperature is above 180°C. Tests performed by Dr. Lee and his team have shown the resulting solder joints also have good to excellent thermal cycling and drop shock performance.
Figures 1-3 show schematically how the melting of the two powders would melt at a peak reflow temperature of 205°C.
Figure 1. Powder A and Powder B at room temperature.
Figure 2. At 205°C, Powder A has melted and it is starting to dissolve to Powder B.
Figure 3. After about a minute at 205°C, Powder B starts to dissolve. Given enough time, it will completely dissolve in Powder A, resulting in a new alloy that has a remelt temperature over 180°C, as well as good to excellent thermal cycle and drop shock performance.
To me, this invention is one of the most significant in SMT in a generation. It could be argued that it is like finding the holy grail of soldering: melting at low-temperature with a service life at high-temperature.
Cheers,
Dr. Ron
PS. I developed an Excel spreadsheet to calculate the use temperatures. It converts degrees C into K. I used it to calculate the use temperatures above. If you would like a copy, send me a note at [email protected].
A trio of recent posts on manufacturing reshoring — or not — caught my eye.
It’s not happening. Writing in Forbes, Workbench chief executive Prince Ghosh points out that the US lacks the human capacity to fully actionize a return of mass production: “US manufacturing still suffers from problems of labor skills and wage costs. Tariffs have succeeded in lowering global dependency on Chinese manufacturing, but they have failed in driving manufacturing back to the US.” He has a point: It took China 20 years to build up the workforce needed to become the World’s Factory, and that’s even with a roughly 800 million or more citizen advantage over every nation but India.
And there’s no assumption investment in the US will go toward the truly leading edge technologies. To wit: If TMSC builds a 5nm semiconductor wafer fab plant in Arizona, as promised, it will still be behind the state-of-the-art 3nm node process expected to be available in 2022.
It’s happening. A more optimistic view comes from Nick Stonnington, a Forbes Councils Member,* says the US “has the potential to be one of the few countries in the world that is essentially self-contained from a manufacturing standpoint.”
“Reshoring US manufacturing,” he adds, “would not only save enormous transportation costs; it would tie up less capital for less time. When you manufacture your product 5,000 miles away, you must spend extra time specializing your process to each market. In contrast, localized production facilitates just-in-time manufacturing, which optimizes workflow to more quickly produce a more specialized product for less capital investment.
It’s happening, but not how you think. In Footprint 2020: Expansion and Optimization Approaches for US Manufacturers, consulting giant Deloitte says “the next shift in manufacturing locations is imminent,” but adds “some 98% of companies surveyed plan to either expand existing sites, or open new facilities, in countries with existing operations. This trend is true for virtually all types of facilities, from production to assembly to R&D. China and the US are anticipated to receive the highest number of existing country expansions.”
One topic, three views. Which do you agree with? And why?
*For the uninitiated, the Forbes Council is basically a network of bloggers who pay Forbes to publish their work. So take that for what it’s worth.
Jerry Falwell Jr. is in the news again, for salacious reasons that have nothing to do with electronics (I hope).
It seems like he’s having a bad week, and I’m certainly not going to pile on.
But mention of his name reminds me of the time I spoke with the son of the famous evangelist, and it was in my professional capacity as an editor, no less.
As I recall, I answered the phone one day — I can’t remember which year it was, but it would have been sometime around 2004 — to find a very professional voice on the line.
“Mr. Buetow?”
Yes.
“Would you have time to speak with Mr. Jerry Falwell Jr.?”
Umm, sure.
When JFJ came on, he was very polite and to the point. A gentleman in our industry — a printed circuit designer — had developed a concept for putting identical components on opposite sides of a board and running vias through to shorten the length of the connections. The designer, with whom I had spoken from time to time over the years, had offered the concept to Liberty University, where Falwell was vice chancellor. Mr. Falwell Jr. wanted my thoughts on whether Liberty should invest the monies to patent the idea.
I don’t recall what I told him, but a check of the USPTO shows that Liberty did follow through. A colleague reminded me representatives from Liberty actually attended PCB West one year as well to promote the mirror pinout concept. Still, I doubt they made much money off the idea, which has been overcome by other advances in component packaging anyway.
Whatever my advice to Mr. Falwell Jr. was, I hope it didn’t put him in a bad position with his trustees. I’m fairly confident it has nothing to do with the predicament he finds himself in now.
And if he calls me again, I’ll still be happy to talk. Provided we stick to electronics.
Readers may remember that I have had an interest in tin pest for some time. Tin pest can occur if nearly-pure tin is exposed to cold temperatures (<13.2oC) for long periods of time. At the end of this post, I provide a short summary of the tin pest phenomenon. See this striking time lapse video of tin pest forming; I assume the time period is over many months.
The reason for this post is that a medieval scholar, Beata Lipi?ska, from Poland is studying tin pest and its effects on medieval culture, most notably in church organ pipes. She has contacted me to see if I can help her find papers that discuss tin pest from a historical point of view. If readers have any references that could help Beata, please contact her directly at [email protected].
Figure 1. Tin pest forms in Sn .05 Cu alloy from Plumbridge. See the paper referenced below.
What is Tin Pest? Tin is a metal that is allotropic, meaning that it has different crystal structures under varying conditions of temperature and pressure. Tin has two allotropic forms. “Normal” or white beta tin has a stable, tetragonal crystal structure with a density of 7.31g/cm3. Upon cooling below 13.2oC, beta tin slowly turns into alpha tin. “Grey” or alpha tin has a cubic structure and a density of only 5.77g/cm3 . Alpha tin is also a semiconductor, not a metal. The expansion of tin from white to grey causes most tin objects to crumble.
The macro conversion of white to grey tin takes on the order of 18 months. The photo, which is likely the most famous modern photograph of tin pest, shows the phenomenon quite clearly.
This photo is titled “The Formation of Beta-Tin into Alpha-Tin in Sn-0.5Cu at T <10oC” and is referenced from a paper by Y. Karlya, C. Gagg, and W.J. Plumbridge, “Tin Pest in Lead-Free Solders,” in Soldering and Surface Mount Technology, 13/1 [2000] 39-40.
This phenomenon has been known for centuries and there are many interesting, probably apocryphal, stories about tin pest. Perhaps the most famous of stories is that of the tin buttons on Napoleon’s soldiers’ coats disintegrating from tin pest while on their retreat from Moscow. Another common anecdotal story during the middle ages was that Satan was to blame for the decline of the tin organ pipes in Northern European churches, as tin pest often looks like the tin has become “diseased”.
Initially, tin pest was called “tin disease” or “tin plague”. I believe that the name “tin pest” came from the German translation for the word “plague” (i.e., in German, plague is “pest”).
To most people with a little knowledge of materials, the conversion of beta to alpha tin at colder temperatures seems counter-intuitive. Usually materials shrink at colder temperatures; they do not expand. Although it appears that the mechanism is not completely understood, it is likely due to the grey alpha tin having a lower entropy than white beta tin. With the removal of heat at the lower temperatures, a lower entropy state would likely be more stable.
Since the conversion to grey tin requires expansion, the tin pest will usually nucleate at an edge, corner, or surface. The nucleation can take 10’s of months, but once it starts, the conversion can be rapid, causing structural failure within months.
Although tin pest can form at <13.2oC, most researchers believe that the kinetics are very sluggish at this temperature. There seems to be general agreement in the literature that the maximum rate of tin pest formation occurs at -30o to -40oC.
I am trying to implement the Pin-in-Paste (PIP) process. The PWB is 63 mils thick, the component pin diameter is 47 mils, the PWB hole diameter is 87 mils, and the PWB pad diameter is 120 mils. I used the Indium StencilCoach software and the result said that I needed a stencil aperture with a 416 mil diameter for the 5 mil thick stencil I was using.
That stencil aperture diameter is way too big. What gives?
Best,
Peter
Dear Peter,
The issue is that your PWB hole diameter is too large. It is 40 mils greater than the component pin diameter. This situation results in a very large amount of solder required to fill the mostly empty PWB hole. See Figure 1. Since solder paste is about 50% by volume flux, quite a bit of paste is often needed to form a good solder joint.
Fig. 1. This figure is a cross-section schematic of a component mounted on a PWB. The fillet, hole, and pin volumes are shown and the resulting solder volume needed. If the component pin is much smaller than the PWB hole diameter, more solder paste will be needed than the pin-in-paste printing process can provide.
Chatting with my friends, Jim Hall and Phil Zarrow of ITM and Jim McLenaghan of Creyr Innovation, they all recommend that the PWB hole diameter be in the range of 10 to 12 mils larger than the pin diameter. In your case, this would be a hole diameter of 58 mils (I chose 11 mils greater than the pin diameter) and a PWB pad diameter of say 80 mils. The software calculates that a stencil aperture diameter of 194 mils is required (see Figure 2). It might be better to choose a square aperture of 172 mils on a side as seen in the output below. If this size stencil aperture is still too large, solder preforms can help. I will discuss using them in a future post.
Figure 2. The right hand column of this figure shows that a round stencil aperture diameter of 194 mils (2 x 97.184, the third cell from the bottom) is required to form a good solder joint in this application. It might be advantageous to use a square aperture of 172 mils on a side, as show in the fourth cell from the bottom in the right column.
By the way, Jim McLenaghan refined some earlier work that resulted in the formula for the fillet volume used in StencilCoach. Zarrow and Hall just released a book called Troubleshooting Electronic Assembly: Wisdom from the Board Talk Crypt. These three folks are some of the most knowledgeable people in electronics assembly today.
