Tag Archives: PCB design

Back in Person

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The Covid-19 vaccine rollout has begun and we can’t wait to get back to seeing old and new friends in person.

To that end, I want to call your attention to the return of PCB East to the Boston area in June.

We will head to Marlboro, MA, for some 55 hours of training across three days (June 15-17) of printed circuit board engineering training. There, SI expert Lee Ritchey will have a couple of tutorials: Printed Circuit Board Stackup Design for High Performance Products, and also Power Delivery System Design.

We also will offer two full days of Rick Hartley, including a brand new talk titled, “PC Board Design for Optimum Fabrication and Assembly.” As Rick notes, Happy Holden has presented at PCB West a few times where he’s explained how fabricators determine pricing for bare boards and how EMS suppliers determine pricing for PCB assemblies. Happy shares what he calls a “Fab and Assembly Report Card,” which is how manufacturers assess and weight the variables that drive cost.

So, for instance, as most readers know, board size is a major cost driver. But, as Rick explains, what most designers don’t know is that aspect ratio of length to width also has a major impact. Two boards with the same number of layers and same number of sq. inches but with a difference in their respective aspect ratios – say one is much longer than wide – will push up the bare board cost. Same with assembly, which has even more cost drivers than does fab. Rick is going to do is discuss these major cost drivers.

Rick also told me that at PCB West he had discussions during the chat sessions with some of the bare board fabricators in attendance. One of them said (I’m paraphrasing here), “At any point in time as many as 90% of our jobs are on-hold, waiting for correction or clarity from the customer, so we can proceed.” In Rick’s opinion, designers are flying blind when it comes to many the cost drivers and what suppliers need at both the bare board and assembly level, hence the reason for so many delayed PCBs. These delays also add cost.

What Rick wants to do is to highlight and talk about the factors that Really drive up cost, like board size and aspect ratio, layer count, Z-axis uniformity, copper balance, etc.

And Susy Webb will have brand new, two-day tutorial for design engineers, “A Comprehensive Guide to PCB Design Necessities.” Her class will feature an overview of the entire process of board design, from start to finish, addressing the EE designing their own boards or the new designer who needs to thoroughly understand all the steps and processes. She’ll cover everything from the electronics and physics involved, how the rise time and controlling the energy fields impact the signals on the board, choosing parts types, schematics and signal and constraint issues, mechanical issues, and so on. Susy is also doing an all-day webinar.

We are looking forward to these any other presentations, and also to the exhibits on Jun. 16. Registration is now open, so visit pcbeast.com for details.

What is Your Supply Chain Telling You about Packages?

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Have you purchased any electronics components lately? Have you tried and failed to do so lately? Allocation is the word of the day and substitutions are your friend.

Many, many parts are in short supply, or unavailable with extraordinarily long lead times. Sure, that happens every now and then in this industry. It’s a periodic nuisance, but what should you do for the long term? We’re are getting some interesting stories from component suppliers that might help. 

What we’re hearing is that many passive manufacturers will be trying to move their customers to smaller sizes. They want to consolidate on as few packages as is possible. That means we may be seeing the end of 1206, 0805, and maybe even 0603 form factors for many passive values.

It kind of makes sense. Right now, there might be several dozen different varieties of 0.1uF, 16V capacitor. Does the industry need that? And if there isn’t enough fab capacity to make all of the variations, why not consolidate and run more of fewer variations? It won’t surprise me if we start seeing fewer voltage ranges as well. In most cases, a 16V part will be just fine if you’re calling for a 6V or 10V part.

The chip industry has been doing this for a while. Many of the newer components just come in BGA or QFN packages. Fewer and few leading edge parts come in large through-hole or SOIC packages.

Consider using smaller components, like standardizing on 0402 parts. I know it can be a pain to use smaller parts, but any potential for future proofing your design now can prevent delays or otherwise unnecessary redesign cycles. You might just be able shrink your board size and save some money on the board fab too.

Keep approved substitutions close by, and look for newer chips that are more likely to stay in production. For microcontrollers, pick parts that have multiple memory capacity or speed range variants all in the same package.

This looks to be a pretty extreme allocation cycle, and I have a feeling that the industry will be different when we come out of it.

Duane Benson
Which is worse
Being the missing link or the weakest link?

 

A Question on Schematic Style

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Just a quick question here…

I’m placing the components for my TinyFPGA based stepper motor controller board (see the prior articles here first, here next, and here last). Specifically, I’m finding places for all of the capacitors. That’s where the question of schematic style comes in. 

When I first started using CAD software, sometime shortly before the stegosaurus roamed the land, I would position component symbols on the schematic near the chips they belonged with. Doing so made it easy, come layout time, to remember which capacitors go where.

Since then, though — and I don’t remember when I started this — I’ve started following the practice of grouping capacitors on the schematic, as I’ve done on this sheet to the right. All of the capacitors are up at the top, shown connected to V+ and ground rails.

That’s not a problem when they’re all 0.1uf bypass capacitors and each chip just takes one. However, with higher speed and more complex chips, multiple bypass caps or different values are often required on each chip.

Now, when I go to layout, I need to go find my component data sheets again (they really should never be very far away) and re-figure out what combinations of bypass capacitors go to which pins on what chips.

I like the cleaner schematic that results from grouping bypass caps, but it’s adds pain and a bit of opportunity for error during layout.

What style do you use and why? Am I an idiot for doing it this way? Wait. Don’t answer that last question.

Duane Benson
Six of one and 12 × 5 × 10-1 of another

Basic Layout — Aligning Components

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Not long ago, I designed an Arduino compatible clock board. The board has 12 NeoPixel (digital addressed RGB LEDs) arranged around the board to act as hour hands. The minutes and seconds are represented by an external ring of 60 NeoPixels.

 

 

 

 

 

 

 

 

 

 

How did I go about positioning the 12 NeoPixels, and what does it matter? For aesthetic reasons, I do want each NeoPixel in the proper place. If any are off a bit, I’ll notice every time I look at the clock.

I created a triangle, with all of the correct distances, and drew in in my CAD software’s Document layer. The Document layer looks just like a silk screen layer, when visible, but it won’t be printed on the board. You can use this layer to put in extra information for yourself, or for the manufacturer.

 

 

 

 

 

 

 

 

 

 

You’ll notice that I also wrote in the document layer “No tabs here.” That’s an instruction to the board fabricator to not put a panel tab where the micro USB connector goes. If it did, the board wouldn’t be buildable when panelized.

Some create a fabrication document layer and an assembly document layer. An example might pertain to reference designators. If the board is too compact for reference designators, of if, for aesthetic reasons, you want to leave them off the finished board, You can put the reference designators in an Assembly Documentation layer. Then be sure to let your assembler know what you’ve done.

The other things I did here is to keep all the LEDs aligned with the baseline of the PCB. In theory, you can place a component at any rotation angle you want. But, like any system, manufacturing works better when there are fewer variables.

You reduce the probability of error if you keep components aligned at factors of 90 degrees. It also helps to keep polarities oriented the same way, as much as possible. For example, if you can, have all the diode polarities facing the same direction.

Duane Benson
Time flies like an arrow; fruit flies like a banana

http://blog.screamingcircuits.com

QFN Center Pad Revisited

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The QFN (quad flat pack, no leads) package can no longer be considered exotic. It was when I first wrote about it a decade ago, but not anymore. In fact, with the wafer-scale BGA, it’s one of the more common packages for new chip designs.

Not all QFNs come with an exposed metal pad underneath, but most do, and that can cause problems with reflow solder. The pad itself isn’t the problem, but improper solder paste stencil layer design can be.

The default stencil layer in the CAD library footprint might have an opening the full size of the metal pad. If that’s the case, modify the footprint so that there will be 50% to 75% coverage with solder paste (Figure 1). If you don’t, it may result in yield problems. With a 100% open area, the likely result is too much solder in the middle. The part will ride up, or float, and may not connect with all of the pads on the sides of the part.

Figure 1

Figure 1. The optimal QFN footprint will have 50% to 75% solder paste coverage.

 

Figure 2 shows a stencil with too large an opening in the center, a segmented paste layer in the CAD footprint, and the resultant segmented stencil.

Figure 2

Figure 2. Stencils shown with too large an opening in the center (left), segmented paste layer (center), and the resultant segmented stencil (right).

 

You may note that I said to shoot for 50% to 75% coverage and ask: “Well, is it 50% or 75%? What gives?”

True, that is a bit of ambiguity. Anything in that range should be fine for prototype boards, however. If the assembly is headed for volume production, work with the manufacturer to tweak the design for best high-volume yield.

The good news on this front is that many QFN manufacturers and parts library creators have taken notice. It’s far more likely now than it was 10 years ago to find a datasheet correctly illustrating this, and footprints created correctly. But, always check your footprints to make sure.

Duane Benson

http://blog.screamingcircuits.com

What Do You Do If You Can’t Have Reference Designators?

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The first answer to that question is probably going to be along the lines of, “Put them on the board.”

But, sometimes you can’t have reference designators on your board. Maybe it’s too densely populated and there isn’t room. Maybe, for aesthetic reasons, you’ve chosen to leave them off. With some products, like development boards, it’s sometimes necessary to use the space for instruction or functional identification and reference designators would confuse your customers. 

It’s always best to put reference designators as close to the part as possible, and on the same side as the part, but if that’s not possible, you can still create an assembly drawing. When laying out the board, put the reference designators in a different layer than the text you want in silk screen. Then, create a PDF that has all the component outlines in their place, with reference designators. Make one for the top and one for the bottom. Call this document “assembly drawing” and include it in the files sent in to be manufactured.

Figure 1 shows a good assembly drawing format. It has reference designators and polarity marks.

You might ask why reference designators are needed when all the surface-mount parts are machine-assembled. First, any through-hole parts are hand-assembled. Their locations and board side needs to be clear for the people stuffing them.

Second, CAD systems don’t always have 100% accurate information. If the center point of the footprint is off, surface mount machines (ours and anyone else’s) will center the part where file says to put it, which, in the case, would be the wrong spot.

The reference designators are also part of quality control. It’s another opportunity to remove ambiguity. Ambiguity bad. Certainty good.

Duane Benson
Car 54, where are you?

http://blog.screamingcircuits.com/

What Route Do You Take?

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There are a lot of polar opposites in the “what is my philosophy” world: Mac vs. PC, on shore vs. off shore manufacturing, Ford vs. Chevy, Atmel vs. Microchip (well, maybe not that one so much any more), auto router vs. hand route…. Yes, I’m specifically avoiding political opposites.

Routing is what I’m really interested in today. The conventional debate is hand vs. auto route. CAD companies spend a lot of time and money on autorouters, but there’s definitely a line of thought that says it’s not ready for prime time yet. This shirt designed by Chris Gammel, on Teespring pretty much says it all.

But, it’s more complex than that. Most auto-routes end up requiring some hand work, either to finish routes that can’t be found automatically, or to clean up a few less than efficient choices. There are differing techniques for complete hand-routing as well.

I often find myself looking at a layout project a bit like a chess game. I don’t just start at one end of the board and work my way to the other side. I tend to focus on specific parts or critical requirements first, like signal paths that need to be short, or sections with more critical grounding requirements. (The image above isn’t mine. It’s from the Beagleboard.)

When it gets to the mass, I tend to try and think ahead, projecting moves out, as though it were a chess game. When I’m looking for the best route for signal path A, I try and think ahead to how it will impact B, D, D… as far ahead as I can go.

I’m not sure if doing it this way is easier, of if it would be better to just start routing and then re-route as I run into roadblacks. What about you? How do you approach a complex layout?

Duane Benson
Holy cow. I Googled “Trust no one” to get some ideas for my signature
Never do that. It’s going to take a week to shake off all the negativity

blog.screamingcircuits.com

Mirror Mirror

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A mirror can bring bad luck, it is said. In this PCB assembly challenge, it certainly did when a mirrored pad layout for a transformer made it impossible to mount the component to its intended location on the top side of a PCB in its usual orientation.

Design error: A mirrored pad layout creates orientation problems between pads and component pins; layout is for bottom-side rather than top-side mounting.

The component’s footprint, it turns out, would work fine if it were on the opposite side of the PCB, but that bottom-side installation is not possible.

Flipped upside down, the SMT transformer’s pins line up fine, except that they are facing upwards. But we can still mount the component and make a robust connection using adhesive and connecting wires.

The customer made a design mistake; although the pads for top-side SMT mounting of the component are in place, they are in mirror-image orientation; e.g., the pad layout with Pin 1 is intended to be installed from the bottom of the board. Consequently, it doesn’t match up in terms of orientation on the top side of the PCB unless the component is literally placed onto its back. But that means that the leads are sticking up into the air, pointing in the wrong direction.

It’s well known that a dab of epoxy can cure a host of ills, and in this case it was simply a matter of dispensing a tiny amount of epoxy onto the back of the component body, in the center, as well as onto its intended location on the SMT PCB assembly.

Small dots of epoxy are applied to the PCB surface and to the component body, before it is attached, the epoxy cured, and the transformer connected pin by pin.

The component is then carefully located in place upside-down and the epoxy cured. With the component robustly mounted in this manner, small wires were then run from each lead (pin) to its corresponding pad on the board’s surface.

It requires skillful hand soldering once the component is in place, but the connection is robust and complete.

 

Roy Akber

www.rushpcb.com

[email protected]

 

Raspberry Pi — What’s It All Mean?

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What would you do with a computer that costs $5?

First, let me explain a bit. The Raspberry Pi, if you don’t know, is a small, inexpensive single board computer designed by the non-profit Raspberry Pi foundation in England. Its mission is to make computer-related education less expensive and more accessible to the masses. As a next step in that mission, it just introduced the Raspberry Pi Zero, with an MSRP of $5. So, you can buy a Big Mac, or a Pi Zero. You could buy some peanut butter, jelly and a loaf of bread, eat that for the next five lunches, and buy five Pi Zeros.

Now some folks have complained that it’s not very useful on its own. It needs a wall bug power supply, a micro SD card, a few cables, and a USB hub to connect a keyboard and mouse to.

That’s true, if you want to use it as a full PC workstation, which you can. It runs the “Raspian” distribution of Linux. But, I don’t think that’s where the greatest potential for this thing lies. No, I wouldn’t use this as a workstation. It’s biggest potential, in my opinion, is as an inexpensive embedded controller.

It has I2C, SPI, and RS232 pins available, as well as plenty of GPIO. Attach a small daughter card with accelerometer, gyro, magnetometer, and GPS, and you’ve got a nice drone auto pilot. Attach a few sensors and a cell phone module, and you’ve got a remote data logger. What would you do with one of these?

Duane Benson
Little Jack Horner couldn’t get a plum out of this pi.

http://blog.screamingcircuits.com/