Tag Archives: PCB design

Heads in the Cloud

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DigiTimes is reporting that companies like Quanta are working with cloud computing developers to offer turnkey solutions, selling storage space to design and manufacturing customers.

What DigiTimes did not report, however, is that such arrangements extend to PCB CAD tool providers. In fact, Quanta is offering one major CAD tool vendor’s PCB software via the cloud. Users can access the tool on a fee for use basis.

What’s scary about this arrangement is the potential for havoc should a dispute arise between Quanta and its customers. Access to designs — in process or legacy — is critical, and if a design needs to be respun at 11 PM on a Sunday night, and the OEM doesn’t have easy access to the server for whatever reason, that’s going to be a problem.

Cadence: All Sync’d Up

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Cadence today announced the release of point revisions to both Allegro and OrCAD, continuing its tradition of keeping releases of its major platforms in sync. They show significant upgrades in timing speeds and simulation speeds, respectively, as well as better use of state-of-the-art collaboration tools.

To the latter point, Hemant Shah, the product marketing manager for Allegro, says the point releases are a reflection of changes Cadence sees in the user base. ODMs are evolving to “parallelism,” he told me. “That’s where we learned the EDA tools were not designed for parallelism and needed to be rethought.” As a result, Cadence adopted Microsoft’s SharePoint collaboration tools, giving users a greater control over different versions and WIP design data management.

It was interesting to hear a major software vendor acknowledge that not everything developed in-house would or could be best in class. Likewise, Shah said that the company’s recent acquisition of Sigrity reaffirms the management’s commitment to the PCB space — something its competitors have questioned from time to time.

He added that the future releases leverage Sigrity’s power and SI technology across both the existing platforms and in Sigrity’s standalone products.

PCB West Next Week

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As most of you (hopefully) know, PCB West is next week. The annual conference and trade show, now in its 21st year, is the biggest and best event for the electronics design, fabrication and assembly in the Silicon Valley.

Here’s what Dave Ryder, president of Prototron Circuits, has to say about PCB West: “We have been coming to this show for a number of years now and we never fail to pick up some very good and productive leads. In fact, last year we were so busy that we barely had time to eat lunch. With all of the PCB designers attending the conference it makes this a great show for us who are in the quickturn prototype business.”

PCB West takes place Sept. 25 to 27 at the Santa Clara Convention Center. The exhibition, which is free to attend (be sure to preregister at pcbwest.com), is Sept. 26. The show floor is sold out. Check it out!

Via in Pad X 8

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Here’s an interesting via in pad case. On the one hand, the footprint is very symmetrical and clean looking. On the other hand, it has open vias in the pads.

At first glance, I thought this was a DIP footprint with extra long pads, but it’s not. It’s for an SMT part. Personally, I would have put mask between the pads. Looking at the rest of the board (not shown), the spacing between pads and mask is pretty wide, so there may be a good reason. I’m not sure though.

Definitely, though, I would not put the vias in the pads like that. Those open vias will cause solder to flow down to the other side of the board, make a mess there and leave the chips without sufficient solder.

Duane Benson
Sucking solder through a straw – or via

http://blog.screamingcircuits.com/

Behind the Sigrity Deal

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Cadence’s acquisition of Sigrity, announced yesterday, is a big deal for reasons beyond the technology being acquired.

Sure, it’s great for Cadence to gets its hands on Sigrity’s power and signal integrity tools.

But what this move also underscores is something of a recommitment by Cadence to its printed circuit board software. You’d have to go back years to find the last time Cadence completed a significant deal in the PCB space (I’m not including, of course, the failed 2008 “attempt” to purchase Mentor, which eventually cost then CEO Michael Fister his job.)

Cadence’s PCB revenue jumped in 2011, growing by our estimates roughly 23% year-over-year. That makes it by far the fastest-growing player in the PCB EDA space. How long has it been since they could say that?

Coupled with its aggressive support of the IPC-2581 data transfer format, Cadence is showing a newfound vigor toward protecting and even extending its circuit board design position. Mentor remains a much larger competitor in PCB sales, but there are signs of a shift taking place.

How Not to Trick Your BGA Friends

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Continuing with yesterday’s theme, I have a couple examples that should have been fine, but due to issues at the board house, improper storage or contamination, ended up very much not fine.

What is wrongBehind door number one, we have an OSP finish that will make you very unhappy. That’s “Organic Solderability Preservatives” in long hand. I’ve also heard it called “Organic Surface Preservative”, but close enough. It is a nice flay surface which is good for BGAs. Years ago, it had a reputation for being poor quality, “cheap”, but newer formulas seem to work pretty good in both leaded and lead free. In this case, the darker pads were likely contaminated in some way – either at the board fab house or subsequently in handling.

Siver migration problemNext is the worst example of surface degradation I’ve ever seen. Yes, it’s an extreme outlier case, but this is where a silver board can go if it wasn’t built with the best quality control, was stored too long, was exposed to polluted air or other contamination and had bad luck. This board probably has all of those issues, but any one alone can be problematic. Silver board especially should be stored in a cool dark place; preferably sealed in the original packaging.

Duane Benson
OSP can also mean Oregon State Patrol, but they don’t care about BGAs. Just safe driving.

http://blog.screamingcircuits.com/

A ‘Hall’ of a Man

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We are thrilled to announce the launch (opening?) of the PCD&F Hall of Fame for PCB Design.

Actually, that’s a misstatement: It’s not called the PCD&F Hall of Fame. It’s the Dieter Bergman Hall of Fame. We are naming it for the longtime technical director of the IPC, and perhaps the leading advocate over the 40 years for the printed circuit board designer. Dieter has led the efforts for a number of design standards, including those for bare board layout, land patterns, data transfer and other critical aspects. More important, he was a vital cog in getting designers the recognition they deserve within their companies, helping to launch and promote the Designer Certification program, and teaching hundreds of workshops around the world.

I recall — it was around 1995 — working the IPC booth at the PCB Design West trade show. I came to man the booth one morning, and noticed some of the standards we left in it the night before were missing. I groused about the sticky fingers that apparently were attending the show. Dieter shook his head. “These designers,” he said, “they are just so thirsty for knowledge.” It didn’t matter if they walked off with some materials without paying; they did so because they wanted to be better at their jobs, and that made it OK.

Dieter’s unwavering loyalty and respect for the profession really opened my eyes. He was right then, and he’s still right now.

CAD tools make design easier and faster, but good design is not button-pushing. Rather, it’s understanding the tradeoffs of materials properties and electrical continuity and speed and manufacturability, and getting the right mix in the most expeditious timeframe possible. A former designer himself, Dieter understood this and has always been willing to speak up to help. It’s an honor to name the Hall after him.

Fiddling with Fiducials Again

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I recently posted a note about fiducials but I didn’t have any images. Here’s a couple of examples:

IPC acceptable fiducialsThis first example shows what IPC would like to see. If this is an individual board, this would be it. If it were part of a panel, you would follow the same pattern on the panel rails and also put it on each individual board in the panel.

As I wrote in the earlier post, we don’t require these, but it’s always a good idea. You’ll need them once you go into volume manufacturing anyway.

The next example won’t make IPC happy, but it will make Screaming Circuits happy:

Also acceptable fiducialsIt only uses two fiducial dots, but it isn’t reversible. Reversibility is okay for jackets, but not for circuit boards. Since one of the dots is offset, it can’t be placed on the machine and recognized as correct in any way except in the proper orientation.

The important aspect of both of these examples is that they remove ambiguity. There can’t be any uncertainty, which is good because uncertainty is your enemy. It’s a subtle enemy. It might not bother you 99.9 times out of a hundred, but then, when you’re not looking, it can strike. So, give a hoot and stomp out ambiguity.

Duane Benson
False data can act only as a distraction. Therefore, I shall refuse to perceive.

http://blog.screamingcircuits.com/

Keepin’ it Smooth: How Surface Roughness Impacts High Performance PCBs

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First a disclaimer: I am not an electrical engineer. I am only fluent in my knowledge of PCB fabrication. In other words, much of what I am about to share is borrowed from well- educated and experienced EEs who don’t share my aversion to math. I am, in effect, jumping into the deep end of the pool, but only because I am wearing my (virtual) brain floaties! For this reason, I ask for your forbearance as I attempt to translate this left-brained subject matter into my right-brained mother tongue. Here we go…

Substrate copper application methods. I have been discussing surface finishes for the last couple of posts, and I would be remiss if I didn’t cover the crucial topic of copper surface roughness and how it specifically impacts high performance PCBs. Most substrates are copper clad with either rolled annealed (RA) copper, electrodeposited copper (ED) or reverse treated copper (RT). I have put some links below should you want to learn more about each type of copper and the resulting surface roughness of each.

When the copper surface is rough, even at microscopic levels, the effective conductor length grows and the resistance increased as the signal must move up and down with the topography of the copper surface. To the naked eye, copper-clad substrate appears very smooth but when you view the surface under magnification, the copper can look like something akin to the Himalayas! For this reason, some choose RA copper that is both smooth and consistent in thickness. RA can be more costly, however, and not an option for all. ED copper has the roughest surface but, depending on the application and speed requirements, may be perfectly adequate. RT copper is smoother, and doesn’t cost more than ED. Yet with RT copper you need to be careful about potential delamination and poor peel strength. Once again, we are back to trade offs and specific design needs!

Rogers has a “LoPro” laminate series that is extremely smooth while Taconic offers an extremely smooth “reverse treated/ED” clad laminate. These laminates aid in good, sharp etch definition as well. In some cases, these are smoother than RA copper and can be less costly.

Skin Effect Considerations

  • Michael Ingham of Spectrum Integrity shared the following illustrations with me in regards to the skin effect and how a signal flows through a conductor. In the first illustration, he shows a rough cross-section of how a very high frequency signal tends to run on the outermost areas of a conductor—creating the skin effect. However, he notes that this is only true when there is not a ground plane underneath.
  • In the second and third simulation illustrations he used a full 3D field solver for a top layer trace that has a ground plane beneath.
  • The second illustration shows how a current will flow through the entire trace cross section area at low frequency.
  • Finally, in the last illustration, he shows the current distribution at 20GHz, which is mostly at the bottom and sides of the trace.

Fig 1 Current Flow

Michael’s point is that when it comes to surface finishes and texture, the most critical issue appears to be the smoothness of the copper. He has raised the question that if the high-frequency current mainly flows on the bottom and sides of a trace—is using nickel really causing the unwanted losses, or is copper roughness the culprit? Many fear using ENIG-plated traces and go to great measures to avoid and resort to using costly mixed plating, etc. Below is measured data of a RF trace with standard ENIG plating. The overall loss may be surprising.

Fig 2 Insertion Loss

This is just scratching the surface (no pun intended!) in regards to the topic of conductor losses and copper profile. When dealing with coupled trace structures, the effects of nickel could have a big impact due to having adjacent trace walls interacting. But I will leave this topic for Michael to cover at another time!

Spectrum Integrity has been very successful in high-speed/high performance designs, and has done so focusing more on design technique and paying great attention to all the properties of materials such as the smoothness of the copper rather than focusing on surface finishes or restricting to very low dielectric loss materials. They have enjoyed very good success with avoiding costly mixed plating and with the use of smooth copper laminates like the Taconic RT/ED material.

When it comes to the smoothness of outer layer copper traces, a board fabricator can go a long way to hurt or help your desired results! The higher the speed/frequency and more critical the application, the more you need to be working with a company like Transline Technology who understands high performance board fabrication. For instance, when we clean the outer surface of the boards, we do it with chemical cleaners that are non-abrasive and maintain the smooth copper outer surface. Additionally, there are many points throughout the manufacturing process where standard practices of PCB handling can also compromise the otherwise smooth copper outer surface that can create havoc for your design performance. High performance boards can appear deceptively simple in their design, but there are many intricate details that must be considered when making a sound high performance board. Many a board fabricator does not possess the knowledge or the trained eye for the subtleties of high performance PCB fabrication.

Conclusion. Skilled and well-informed partners are the key to success when it comes to choosing surface finishes and materials for high performance designs. These issues are complex and have many nuances that must be considered to create successful products. As such, it is critical to forge strong working relationships with both your advanced material suppliers and your board suppliers. By doing so, you will save much time and money and avoid a host of needless headaches. I have listed some additional resources below. Many thanks to Michael Ingham of Spectrum Integrity, who is always teaching me something! I highly recommend Spectrum Integrity for RF/MW and high performance design. Their website link can be found below. As always, I welcome your input and comments! [email protected]

I also invite you for lively discussion regarding High Performance board design and fab on Linked In: http://tinyurl.com/85ymddk

–Judy

 

Additional Resources

http://tinyurl.com/7he2lmv

http://tinyurl.com/7wnewcq

http://www.polarinstruments.com/support/si/AP8155.html

http://tinyurl.com/7yblg4m

http://www.spectrumintegrity.com/

http://www.rogerscorp.com/documents/1183/acm/RO4000-LoPro-Laminates.aspx

http://www.taconic-add.com/en–products–material-view.php