Tag Archives: solder mask

0.4mm Pitch BGA Redux

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I’ve written about it before, and again here.

When dealing with new technology parts, it’s really important to look up all of the manufacturer’s component information that is available. I’m going to quote from the Texas Instruments document “PCB Design Guidelines for 0.4mm Package-On-Package (PoP) Packages,” Section 10 (PDF page 8):

Industry reliability studies have revealed that NSMD-type pads are highly recommended for most 0.5mm pitch BGA applications. However, there is a problem with this approach at 0.4 mm pitch.

Real-world assembly experiments with the BeagleBoard and the OMAP35x EVM revealed a tendency for solder bridging between pads when NSMD were used. There was insufficient solder mask webbing between the pads to ward off bridging. Therefore, a SMD design was used which resulted in much better assembly yields with no solder bridging.

If you are using a 0.4 mm pitch BGA with the balls aligned in a grid (as opposed to staggered), read the design guidlines from the manufacturer before laying out the board.

In a presentation about the development of the Beagleboard, Gerald Coley, Beagleboard designer, notes that their first two runs had non soldermask defined pads, resulting in a 10% yield. After another run of PCBs where the pads on the PCB were the same size as the pads on the device and the PCB pads were soldermask defined, yields rose to 96%. And verify that your PCB house does in fact follow your instructions. Some will think they know better and will change the mask layout.

If you are still unsure or think your design will have different requirements, call an applications engineer at the component manufacturer and discuss your project and the layout.

Duane Benson
Trust but verify

http://blog.screamingcircuits.com/

Little Chippy Challenges

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And “chippy,” in this context, refers to chip caps and any other tiny two-connector components. When considering surface mount, most people think of the many-connector parts, like BGAs and QFNs as the challenging components. That’s mostly true. However, the little passives can be big bears too if not treated properly.

Two part tombstone You could have tombstoning problems. This can be caused by unequal sized pads, unequal sized traces going to the pads or inequality in copper plane in a different layer. A big part on one side can cause tombstoning too — the big part’s thermal mass may slow the solder paste melt on one side of the part, leading to tombstoning.H Skewed passive via in pad

Via-in-pad is still a problem too. Open vias can lead to unreliable connections, tombstoning or crooked  parts.

Soldermask tombstoning for blog Solder mask can cause problems too. Too thick a solder mask can prevent the part from reaching the solder and can cause tombstoning. Too think a solder mask can also interfere with outgassing in the reflow oven which can cause solder ball splatter. (A = okay, B = not okay).

Duane Benson
It just goes to show you…
It’s always something.

http://blog.screamingcircuits.com/

Pad is as Pad Does

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I’ve recently written a bit about solder mask and pads relative to BGAs. In most cases, we recommend NSMD (Non Solder Mask Defined), or copper pad defined, pad for BGAs. With the BGAs, the NSMD pads will permit the BGA to sag just a bit more and adhere to both the top and the sides of the pad, resulting in a better mechanical connection. The exception seems to be 0.4mm pitch BGAs with a straight matrix alignment as in the illustration the link above. TI, with its Beagleboard project, found that NSMD pads tended to lead to bridging and had much better results with SMD pads. Staggered BGA lands should still use NSMD pads though.

Along with the 0.4mm BGAs, not all parts need or want NSMD pads. International Rectifier has a package called “DirectFET” which is designed to use solder-mask-defined layouts. In this package, the FET source and gate connections are directly on the FET die. The drain connection is a plated copper can directly bonded to the drain side of the silicon die. This system gives a very low-loss capable part with great thermal conduction properties.

Internal Rectifier recommends solder-mask-defined pad layouts. Take a look at their application note 1035 for complete details on designing with this package. I might try the form-factor out myself some time. It always bugs me that a 100 Amp MOSFET might only, in practice, be able to pass a small chunk of that amount of current because the leads or internal interconnects would otherwise melt. The DirectFET package should aleviatemuch of the melting problem.

Duane Benson
Melting is good if you’re talking about toasted cheese

http://blog.screamingcircuits.com/

Mask Control

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I wonder. Is solder mask difficult to control in most CAD packages? Or do we just not need to control it very often so we forget? Take this little footprint here. Oval pad

It looks like someone just used a little flood fill to create the thermal pad rather than creating a new custom footprint. That would have been fine except that the flood fill area has solder mask on it.

In Eagle, if you want to keep the mask off of an area that would other wise have mask, you draw a polygon in layer 29, tStop (or 30 bStop for the bottom) over the are you want to keep mask off of. Not difficult, but not necessarily obvious either. With Sunstone PCB123, you pretty much do the same thing with the SS Top or SS Bottom layers. I don’t know about any other packages, but I would guess it would be a similar approach.

Of course, just making the footprint with the library package editor would take care of it too, but sometimes it’s just more expedient to take a footprint that’s close and mod it up with a polygon or something similar.

Duane Benson
Is Oregon like a Polygon?
No, because it hasn’t “gone” anywhere

http://blog.screamingcircuits.com/

Tented QFN/QFP Via-in-Pad

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Below is a pretty decent example of mask-tented vias in the thermal pad of a QFP. Most manufacturers recommend no more then 100 – 125 microns wider than the via to minimize voiding and thermal insulation in cases like this. This is a reasonably inexpensive way to handle vias in the thermal pad. Sometimes though, the tents will pop open, allowing solder to wick down through the via.

The mask over the center via on the right looks a little thin, so you’d want to give it an extra look over after reflow to make sure it’s okay. (We’d do that here, of course.)

We’d rather not see this technique on really small parts because it gets difficult for the fabricator to put down the mask with enough precision. With small parts, filling and plating over the vias is the preferred technique. Well, that’s always the preferred method. It’s just more important with smaller parts and BGAs. This method is acceptable for most QFPs and larger QFNs, though.

Duane Benson
All your via are belong to us

http://blog.screamingcircuits.com/