Tag Archives: solder voids

Measuring Void Content

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A reader writes: Dear Dr. Ron, I need to measure the void content of an alloy. Is there an easy way to do it?

After a little thought, it occurred to me that the densities of the voided and unvoided material will likely hold the answer. I derived the result below. Assuming we know the density of the unvoided material, we can measure the density of the voided material with the Wet Gold Technique, discussed in recent posts, if the voids are not connected (closed cell.)  If the voids are connected (open cell), you could machine the foam to the shape of a rectangular parallelepiped and determine the density of the foam as the mass divided by the volume.

As an example, let’s say you have a closed cell aluminum foam. We use the wet gold technique to measure its density at 1.5g/cc. The density of solid Al is 2.7g/cc.

So the volume fraction of voids is:

Sadly, this technique could not be used to find void content in solder joints, or in BTC (e.g., QFN) thermal pad connections (which are so handily mitigated by using solder preforms.)  The derivation for the above equation follows:

 

Best Wishes,

Dr. Ron

Small Open Vias

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Pad parts change and so do vias. Our standard policy here is that open vias in pads are bad. We from time to time recommend ways to plug them. Generally, you have several options. Like this post shows. However, with vias in the pads of really small parts, those solder mask options will probably not work. Solder mask generally isn’t put down with enough precision to cover holes on tiny pads, and further, the solder mask would probably mess with the clearance. On the left is an example of a small QFP with open vias in the pads. Those are some small vias.

So, if solder mask isn’t going to work, what QFN center void open vias will? Filling and plating over them. That’s what will work. You really only have two choices: fill and plate, or live with a bunch of voids under the part and solder slopped on the bottom side of the PCB.

Here on the right are two illustrations representing the issue. In the top half of the image on the right, I’m representing the vias with copper plugs and plated over at the board fab house. As with all parts of this sort, there may still be tiny voids. IPC and the manufacturer will have guidelines on the maximum allowable voiding. On the bottom, you see what happens with the vias left open. You get two problems: big voids and solder on the underside of the PCB.

Certainly there are some applications where this doesn’t matter. That’s why there is a second choice: “Live with a bunch of voids and slopped solder.” If you can’t live with voids and solder slop, you have to bite the bullet and pay the extra for a PCB with filled vias. Board houses that do this have a variety of materials to use including copper, electrically conductive epoxy and thermal conductive epoxy.

Duane Benson
Please sir, may I have some more voids?
No! No voids for you!

http://blog.screamingcircuits.com/